Unter HDI-Leiterplatten verstehen wir Leiterplatten mit hochdichter Verdrahtung, gekennzeichnet durch technische Merkmale wie z.B. Leiterbahnstrukturen ≤ 75 μm und Sackbohrungen (blind vias), sowie vergrabenen Bohrungen (buried vias). Diese Mikrobohrungen werden sowohl mechanisch als auch in Lasertechnologie ausgeführt. Als zusätzliche Option bieten wir an, Bohrungen zu pluggen und gegebenenfalls zu überkupfern, bzw. mit Kupfer aufzufüllen.
TELECOM 8 Layer HDI / S1000-2 (Hi-Tg FR4)
• 5.1" x 7.5" (130 x 191mm)
• Thickness .047 (1.2mm)
• Construction 3+N+3
• Aspect Ratio 12:1
• Microvias L1-L2, L2-L3, L7-L6, L8-L7; Buried vias L3-L6
• Via-in-Pas (VIPPO)
• 12 impedance controlled lines (SE/DIFF)
• Min L/S .004" (.10mm)
• Drill/Pad .004"/.010" (.10/.25mm
• ENIG Finish
Technologie Roadmap (1)
| inch [mm] | Standard 2016 |
Advanced 2016 |
Emerging 2016-2017 |
Future 2018 |
|
| Key Attributes | Layer Count | Up to 10L | 12L to 16L | 18L to 24L | >24L |
| Max Thickness | 0.079." [2.00] | .125" [3.18] | .150" [3.80] | 0.200“ [5.08] | |
| Largest Panel | 24”x18”[610x455] | 24”x18”[610x455] | 24”x18”[610x455] | TBD | |
| Minimum Line & Space ½ oz Base I/L,O/L (E&F ¼oz Base) |
Line Width | .005" [.127] | .004" [.10] | .003" [.076] | .002" [.05] |
| Line Space | .005" [.127] | .004" [.10] | .003" [.076] | .002" [.05] | |
| Tolerance | ±.0004" [.010] | ±.0004" [.01] | ±.0004" [.01] | ±.0004" [.01] | |
| Drilled Vias Size | Drill Size | .012" [.30] | .010" [.25] | .008 [.20] | .006" [.15] |
| Pad Diameter | +.010" [.25] | +.008" [.20] | +.006" [.15] | .006" [.15] | |
| Aspect Ratio | 8:1 | 12:1 | 16:1 | 20:1 | |
Technologie Roadmap (2)
| inch [mm] | Standard 2016 | Advanced 2016 |
Emerging 2016-2017 | Future 2018 |
|
| Via Structures | Microvia layers | Mechanical HDI | 1+N+1 | Laser 1+N+1 | 2+ or above |
| Buried Subs | No | Yes | Yes | Yes | |
| Stacked Microvia | No | Yes | Yes | Yes | |
| Microvias | Min Via Size | .006" [.15] | .004" [.10] | .003" [.076] | TBD |
| Pad Diameter | +.018" [.46] | .004" [.10] | .003" [.076] | TBD | |
| Aspect Ratio | .7:1 | .7:1 | 1:1 | TBD | |
| Conductive & Non- Conductive Via Fill |
Min Hole Size | .012" [.30] | .010" [.25] | .008 [.20] | <.008" [.20] |
| Aspect Ratio | 8:1 | 10:1 | 10:1 | TBD | |
Technologie Roadmap (3)
| inch [mm] | Standard 2016 | Advanced | Emerging | Future | |
| Soldermask | Registration | ±.004" [.10] | ±.002" [.05] | <±.002" [.05] | Tangency |
| Min Opening | .020" [.50] | .010" [.25] | .008" [.20] | TBD | |
| Dam Min Width | .004" [.10] | .0035" [.089] | .003" [.08] | TBD | |
| Surface Finishes | ENIG, OSP | ENEPIG | Thick Gold | TBD | |
| Im Sn, Im Ag | Wire Bondable Gold | Multiple Finishes | |||
| HASL | Multiple Finishes | ||||
| Gold Body | |||||
| Material Options | Hi Tg FR-4 | IS 415 | RO4350/4003 | TBD | |
| FR408/408HR | Nelco-13 EP/SI | RF35/TLX/TLY | |||
| Low Dk/Low Df | V Low Dk/ V Low Df | Polyimide | |||
| Halogen Free | New Gen HF | FR4 Hybrids | |||
Technologie Roadmap (4)
| inch [mm] | Standard 2016 | Advanced | Emerging | Future | |
| Controlled Impedance Tolerance | ± 10% | ± 8% | ± 5% | <± 5% | |
| Drill to Copper | .008" [.20] | .007" [.178] | .006" [.15] | <.006" [.15] | |
| Min Annular Ring Tangency | Drill+.010"[.25] | Drill+.008"[.20] | Drill+.006"[.15] | Drill+.006"[.15] | |
| Feature to PCB Edge | .010" [.20] | .008" [.20] | .006" [.15] | <.006" [.15] | |
| Hole to PCB Edge | .010" [.25] | .008" [.20] | .006" [.15] | <.006" [.15] | |
| Rout Tolerance | ±.008”/.004" [.20/.10] | ±.006”/.004" [.15/.10] | ±.004”/.004" [.10/.10] | <.004”/.004" [.10/.10] | |
| Sequential Lamination | No | Yes | Yes | Yes | |
| Backdrilling | No | No | Yes | Yes | |
| Backdrill Tolerance | No | No | ±.005" [.13] | ±.004" [.10] | |